Trends in power semiconductor devices have frequently targeted soft turn-off characteristics under switching transient conditions in order to minimize oscillations and reduce electromagnetic interference while also ensuring no peak overshoot voltages occurring during switching. The device softness can be associated with the total charge (excess carriers) remaining at the final phase during device turn-off. Low levels of charge or the sudden disappearance of charge while the device is turning off and while still conducting relatively high currents (>1 Amp) can result in large oscillations and/or an overshoot voltage which can exceed the device safe operating blocking voltage margin and thus result in device failure. The occurrence of large oscillations and/or an overshoot voltage due to low levels of charge or the sudden disappearance of charge while the device is turning off and while still conducting relatively high currents can be referred to as device snappy characteristics. The disappearance of charge is also related to the punch through voltage Vpth of the device when the space charge region reaches the buffer region sweeping out all the remaining carriers stored during forward conduction. The Vpth value is dependent on the base region thickness and resistivity and is normally close to the nominal DC link value (i.e. half the rated voltage) for medium to low voltage devices (<2000 V) and much lower for high voltage devices, which specify high resistivity base regions (>2000 V). The Vpth is higher for thicker and/or lower resistivity base regions. To increase device softness, a number of conventional design technologies have been implemented in power devices as follows:                Increasing the punch through voltage by choosing thicker and/or lower resistivity base regions if permitted. An extreme example is the Non-Punch-Through (NPT) design. This approach can result in higher losses and high cosmic ray failure rates.        Introducing deep and low-doped buffer profiles to store charge in the higher doping parts of the buffer where the space charge region cannot reach in order to provide carriers for soft turn-off. The softness provided by using such buffer designs has shown limited effect under extreme switching conditions. Examples for such devices are devices with soft-punch-through (SPT) buffers.        Increasing the injection efficiency of the anode region in bipolar devices to provide additional excess carriers for softness. This practice can result in high turn-off losses and limits the device usage to low frequency applications.        
Nevertheless, all the above technologies have proven to be ineffective in preventing snappy characteristics, since snappy behavior has persisted in modern low loss technology designs, which are normally based on very low punch-through voltage values due to the thin and high resistivity base regions. Furthermore, such designs can be very sensitive to extreme test conditions, which increase the tendency towards device snappy recovery including low currents, high dc-link voltages, low temperatures, high commutating current levels, and high stray inductance values.
An existing technology for achieving soft recovery performance in diodes has been implemented which includes highly doped P+ regions in an alternating arrangement with the N+ cathode regions of the main diode. The operating mechanism of this technology is based on the returning electrons during diode reverse recovery, which will flow near the P+N junctions towards the N+ cathode regions. This results in an increased lateral voltage drop at the P+N junctions which will exceed the built-in voltage of the P+N junction, hence causing hole injection from the P+ region. The injected or induced holes will provide charge for soft performance during the latest stages of reverse recovery independent of the device base region and buffer design parameters. Such designs included deep diffused, i.e. several microns thick, and highly doped alternating P+ and N+ regions with wide, i.e. larger than 500 μm, P+ region dimensions. It was also possible to have the P+ regions deeper than the N+ regions to increase the lateral electron flow and subsequent hole injection. The design has only been implemented for silicon fast recovery diodes since the basic principle and process was thought to be only applicable to bipolar devices with N+ cathode regions, i.e. diodes.